Mentor Graphics Enterprise Verification Platform Produces Fresh Levels of Spectacle and Low Power Verification Productivity – Mentor Graphics

  • Questa®, Simulation regression test speeds improved by up to 4X
  • Questa Simulation with Visualizer&trade, Debug Environment 2-5X quicker and smaller
  • Questa Verification Management coverage data collection up to 10X quicker
  • Questa Formal Apps enlargened spectacle by up to 8X
  • Questa Power Aware introduces leading support for UPF Two.1

Mentor Graphics Corporation (NASDAQ: MENT) today announced enhancements to the Mentor®, Enterprise Verification Platform (EVP) that suggest fresh levels of spectacle and productivity across the platform in simulation, debug, formal, coverage closure and low power verification.

The cornerstone of the Mentor EVP, the Questa Simulation engine, now runs up to 4X swifter by improvements in both raw VHDL/Verilog spectacle and incremental flows, coupled with a fresh checkpoint/restore/modify/run flow which saves hours on each long simulation that can share a common &ldquo,setup&rdquo, time before unique stimulus is applied. The Questa Simulation engine has also been enhanced with fresh native Questa rapid logging technology which enables debug mode simulations to run 2-4X quicker and require up to 3X less memory. It deploys &ldquo,brainy&rdquo, reconstruction technics when coupled with the Visualizer Debug Environment, which also significantly reduces debug file sizes. The combination of Questa Simulation and Visualizer Debug provides users the fastest debug turnaround times available on the market today.

&ldquo,After just a few months of use, Visualizer has led to dramatically improved verification spectacle,&rdquo, said Ramesh Shanmugam, Pixelworks senior manager of verification and methodology. &ldquo,This is largely because the way it&rsquo,s used &mdash, for post-processing analysis of simulation data &mdash, is a much more efficient, higher-throughput means of debugging than using a simulator in interactive mode&rdquo,

In coverage-driven verification flows, often the time it takes to merge coverage results from hundreds if not thousands of individual tests can be a major verification spectacle bottleneck. The Questa Verification Management now collects and analyzes coverage data up to 10X quicker with enhanced merging and ranking technology. It quickly generates a unified coverage database (UCDB) that can be accessed by the Accellera UCIS standard interchange format, enabling users to quickly assess their current quality of verification and reduce their coverage closure time.

The Questa Formal engine, now up to 8X swifter, speeds up verification with its enlargening number of formal apps such as clock domain crossing (CDC), property checking, X-state analysis, connectivity checking, and security checking. The Questa Formal works seamlessly with and flawlessly complements the Questa Simulation such that the spectacle improvements to both engines produce swifter overall time to results, and enables customers to pull in their verification schedules and improve end-product quality.

The Questa Power Aware Simulation, the fastest native UPF/RTL simulator, announces its first-to-market support of IEEE 1801 UPF Two.1. The Questa Power Aware includes automatic static and dynamic low power UPF checks that help user quickly verify that their UPF-derived power management structures and behaviors are correct, and automatic UPF-driven coverage and testplan generation that will help users understand and track exactly what is needed for accomplish low power coverage closure. The Questa Power Aware can also now generate functionally-equivalent UPF 1.0 from UPF Two.1 in order to support UPF-based flows with downstream instruments that do not yet fully support UPF2.1 enabling users to take advantage of more productive low power verification methodologies.

For power-aware debug, the Visualizer Debug Environment provides a finish set of windows that enable users to see all UPF-generated structures, power domains, source/sync crossings, isolation, shifters, etc. plus any UPF violations and waveforms of corruptions in one device. Its unified schematic views and highlights of UPF instrumentations directly in the RTL source help verification engineers lightly understand and explore the power management structures within the context of the RTL design.

&ldquo,Our customers request high-performance verification engines that achieve the fastest results in all facets of the verification flow: regression testing, debug and coverage,", said John Lenyo, vice president and general manager, Design Verification Technology Division, Mentor Graphics. &ldquo,The Mentor Enterprise Verification platform produces best-in-class spectacle, productivity and low power analysis in a single, integrated verification platform.&rdquo,

The latest simulation spectacle, productivity and low power verification gains are available in the Questa Ten.Four release that is available instantly.

(Mentor Graphics, Mentor and Questa are registered trademarks and Visualizer is a trademark of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.)

For more information

Related Products

Questa®, Advanced Simulator

Combines high spectacle and capacity simulation with unified advanced debug and functional coverage capabilities for the most accomplish native support of Verilog, SystemVerilog, VHDL, SystemC, SVA, UPF and UVM. Learn More

Questa®, Formal Verification

Questa Formal Verification complements simulation-based RTL design verification by analyzing possible behaviors of the design to detect reachable error states Learn More

Questa®, Power Aware Simulator

Questa Power Aware Simulator enables design teams to verify the architecture and behavior of active power management planned for the implementation. Learn More

Questa®, Verification Management

Questa offers a comprehensive treatment to verification management with a scalable and modular solution. Learn More

Visualizer™ Debug Environment

Visualizer Debug Environment automates debugging for the digital design and verification of today’s complicated SoCs and FPGAs. Learn More

About Mentor Graphics

Mentor Graphics Corporation is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronic, semiconductor and systems companies. Established in 1981, the company reported revenues in the last fiscal year in excess of $1.24 billion. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777.

Fabless/Foundry Ecosystem Solutions Press


True Costs of Process Knot Migration

Determining when and how to make a process knot transition is critical to business success. The solution that requires the least amount of total switch&mdash,in the form of license configurations, required. View White Paper

Dual Patterning Error Visualization for Advanced Knots

Enlargened complexity of Double penetration rules at advanced knots is driving the need for EDA instruments that can not only process more complicated Double penetration constraints, but also enhance error visualization and debugging capabilities. View White Paper

  • Intel Custom-made Foundry Certifies Mentor Graphics Physical Verification and Circuit Simulation Contraptions for 10nm Tri-Gate Process

©, Mentor, a Siemens Business, All rights reserved

Related movie: Trading is 95% mental, macro understanding is everything.

Related movie: Bittrex Verification Basic Upgrade, बिट्रिक्स पर मोबाइल वेरिफिकेशन कैसे करते हैं? By Dinesh Kumar

You may also like...

Leave a Reply

Your email address will not be published. Required fields are marked *